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integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 1 17 / jan / 02 toshiba corporation t oshiba risc processor tmp r 492 7atb-200 (64-bit risc microprocessor) 1. general description the tmpr4927 atb , to be referred as tx4927 mips risc micro - controller is a highly integrated assp solution based on toshiba ? s tx49 /h2 processor core, a 64-bit mips i ,ii,iii isa instruction set architecture (isa) compatible with additional instructions. the t x 4927 is a highly integrated device with integrated peripherals such as sdram memory controller, pci controller, pio, ac-link, uart and timer. this class of product is targeted for applications that require a high performance and cost-effective solution such as networking and printers. 2. features tx49/h2 core with an integrated ieee 754-compliant fpu for single- / double-precision operations 4-channel sdram controller ( 64-bit 100mhz ) 8-channel external bus controller 32-bit pci controller ( 32-bit 33 / 66 mhz ) 4-channel direct memory access ( dma ) controller 2-channel serial i/o port parallel i/o port (up to 16-bit) 3-channel timer / counter ac-link ( ac97 interface ) low power dissipation ( typ. 1.5 w ) the tx4927 operates with the 1.5v int. and the 3.3v i/o, while supporting a low-power ( halt ) mode. cpu maximum operating frequency: 200 mhz ieee1149.1 (jtag) support: debug support unit ( enhanced jtag ) 4 20-pin tbga the information contained herein is subject to change without notice. toshiba is continually working to improve the quality and the reliability of its products. nevertheless , semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also , please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 2 17 / jan / 02 toshiba corporation 2.1 internal block diagram figure 1 shows the tx4927 internal block diagram. figure 1 t x 4927 internal block diagram biu mac fpu mmu clock generator ( pll ) wb tx49 /h2 cpu core i$(32k) gpr d$(32k ) iu debug (dsu) timer uart external bus interface sdram c dmac irc g i b u s im bus bridge pio pcic external bus controller 64bit gbus im bus aclc
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 3 17 / jan / 02 toshiba corporation 2.2 system block diagram figure 2 shows the system block diagram with tx4927. figure 2 typical t x 4927 system block diagram rom/ flash/ sram control signals ext. i/o dev. sdram memory devices pci devices sdram control signals biu mac fpu mmu pll wb tx49 /h2 cpu core i$(32k) gpr d$(32k) iu debug (dsu) timer uart external bus interface sdram c dmac irc g i b u s im bus bridge pio pcic external bus controller 64bit gbus im bus external system bus ( data : 64bit, address : 20bit ) pci bus 32 user logic pcic aclc
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 4 17 / jan / 02 toshiba corporation 2.3 tx49 /h2 core block diagram figure 3 shows the internal block diagram of the tx49 /h2 core integer unit cp0 cp0 registers mmu/tlb exception unit pipeline control gpr data path mac tx49 /h2 core d ebug s upport u nit write buffer 32kb 4 - way set data cache 32kb 4 - way set instruction cache cp1 fpu figure 3 t x 49 /h2 core block diagram 2.4 tx49/h2 core features the t x49/h2 core is high performance and low-power 64-bit risc processor core developed by toshiba. 64-bit operation 32, 64-bit integer general purpose registers 32-bit physical address space and 64-bit virtual address space optimized 5-stage pipeline instruction set mips i, ii , iii compatible isa pref (prefetch) and mac (multiply/accumulate) instructions. 32k byte instruction cache, and 32k byte data cache 4-way set associative with lock function mmu (memory management unit) : 48-entry fully associative jtlb the on-chip fpu supports both single- and double-precision arithmetic, as specified in ieee std 754. on-chip 4-deep write buffer enhanced jtag debug feature built-in debug support unit (dsu)
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 5 17 / jan / 02 toshiba corporation 2.5 t x4 927 peripheral circuit features n external bus controller ( ebusc ) the external bus controller generates necessary signals to control external memory and i/o devices. 8 channel s of c hip select signals, enabling control of up to eight devices supports access to rom ( including mask rom, page mode rom, eprom and eeprom), sram, flash rom, and i/o devices supports 32-bit, 16-bit and 8-bit data bus sizing on a per channel basis supports select ion among full speed ( uo to 100mhz ), 1/2 s peed ( up to 50mhz), 1/3 speed ( uo tp 33 mhz ) and 1/4 speed ( up to 25mhz) on a per channel basis support specification of timing on a per channel basis the user can specify setup and hold times for address, chip enable, write enable, and output enable signals s upport s memory size s of 1m byte to 1g byte for devices with 32-bit data bus, 1m byte to 512m byte s for devices with 16-bit data bus, and 1 m byte to 256m bytes for devices with 8-bit data bus n dma controller ( dmac ) the tx4927 contains a 4-channel dma controller that executes dma transfer to memory and i/o devices. 4-channel i ndependent ly handling internal / external dma requests supports dma transfer with built-in serial i/o controller and ac-link controller based on internal dma requests supports signal address ( fly-by dma ) and dual address transfers in external i/o dma transfer mode using external dma requests supports transfer between memory and external i/o devices having 32 / 16 / 8-bit data bus supports memory-to-memory copy mode, with no address boundary restrictions supports burst transfer of up to 8 double words for a single read / write supports memory fill mode, writing double-word data to specified memory area supports chained dma transfer
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 6 17 / jan / 02 toshiba corporation n sdram controller ( sdramc ) the sdram controller generates necessary control signals for the sdram interface. it has four channels and can handle up to 2g bytes ( 512 mb/channel ) of memory by supporting a variety of memory configurations. memory clock frequency : 50 to 100mhz 4 sets of independent memory channels supports 16m / 64m / 128m / 256m-bit sdram with 2/4 bank size availability support s use of registered dimm supports ecc or parity generation / check functions supports 64 / 32 -bit data bus sizing on a per channel basis supports specification of sdram timing on a per channel basis supports critical word first access of tx49/h2 core low power mode : selectable between self-refreshing and pre-charge power-down n pci controller ( pcic ) the tx4927 contains a pci controller that co mplies with pci local bus specification revision 2.2. compliance with pci local bus specification rev ision 2 .2 32-bit pci interface featuring maximum pci bus clock frequency of 66mhz supports both target and initiator functions supports change of address mapping between internal bus and pci bus pci bus arbiter enables connection of up 4 external bus masters supports booting of tx4927 from memory on pci bus 1 channel of dma controller dedicated to pci controller ( pdmac ) n serial i/o controller ( uart ) the t x 4927 contains a 2-channels asynchronous serial i/o interface ( full duplex uart ). 2 -channel full duplex uart built-in baud rate generator fifos 8-bit x 8 transmitter fifo 13-bit ( 8 data bits and 5 status bits ) x 16 receiver fifo supports dma tranfer
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 7 17 / jan / 02 toshiba corporation n timers / counters controller ( tmr ) the tx4927 contains 3-channel ti mer / c ounter s . 3-channel 32-bit up-counter supports three modes : interval timer mode, pulse generator mode, and watchdog timer mode 2 timer output pins 1 count clock input pin 1 external watchdog reset signal n parallel i/o ports ( pio ) the t x 492 7 contains 16-bit parallel i/o ports ( including 8 bits shared with cb [ 7 : 0 ] ). independent selection of direction of pins and output port type ( totem-pole or open-drain outputs ) on a per bit basis . n ac-link controller ( aclc ) the t x 492 7 contains an ac-link controller, which can be operated using any audio and / or modem codecs described in audio codec ? 97 revision 2.1 ( ac ? 97 ) . supports up to two codecs supports recording and playback for right and left 16-bit pcm channels supports playback for 16-bit surround, center, and lfe channels supports audio recording and layback at variable rate supports line1 and gpio slots for modem codec supports ac-link low power mode, wakeup, and warm reset supports input / output of sample data by dma transfer
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 8 17 / jan / 02 toshiba corporation n i nterrupt controller ( irc ) the tx4927 contains an interrupt controller , which receives interrupt requests sent by both the tx4927 ? s built-in peripherals and external devices and issues interrupt requests to the tx49/h2 core. it has a 16-bit flag register to generate interrupt requests to external devices or the tx49/h2 core. supports 18 internal interrupt sources from built-in peripherals and 6 external interrupt signal inputs 8 interrupt priority levels for each interrupt source supports selection between edge- and level-triggered interrupt detection for each external interrupt 16-bit read / write flag register for interrupt requests, making it possible to issue interrupt request to external devices and to the tx49/h2 core ( irc interrupts ) n extended ejtag interface the tx4927 contains an extended enhanced joint test action group ( extended ejtag ) interface, which provides two functions : jtag boundary scan test that complies with ieee1149.1 and real-time debugging using a debug support unit ( dsu ) built into the tx49/h2 core. ieee 1149.1 jtag boundary scan real-time debugging functions using special emulation probe : execution control ( execution, break, step, and register / memory access ) and pc trace
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 9 17 / jan / 02 toshiba corporation 3. pins 3.1 pin designations a1 pio[1] b17 pciad[0] d7 ce[0]* e23 pciad[22] j25 gnt[0]* a 2 pio[0] b18 pciad[3] d8 vddin e24 pciad[21] j26 pciclk[1] a 3 swe* b19 pciad[6] d9 vss e25 pciad[20] k1 reset* a 4 ce[ 7 ]* b20 pciad[8] d10 vddin e26 pciad[19] k2 test[0]* a 5 ce[ 5 ]* b21 pciad[12] d11 dmaack[0] f1 int[2] k3 haltdoze a 6 c e[4]* b22 c_be[1] d12 vddio f2 int[1] k4 vddin a 7 dmaack [2] b23 perr* d13 tpc[2] f3 int[0] k5 vss a 8 dma ack [1] b24 stop* d14 vddio f4 nmi* k22 vss a 9 bwe [0] * b25 frame* d15 vddin f5 vddin k23 vddin a 10 bwe[1] * b26 vss d16 vddio f22 vddio k24 gnt[1]* a11 eeprom_di c1 pio[5] d17 vddin f23 c_be[3] k25 req[0]* a 12 eeprom_do c2 pio[4] d18 pciad[4] f24 id_sel k26 pciclk[2] a 13 vss c3 vddio d19 vddio f25 vddio l1 sysclk a 14 eeprom_sk c4 ack* d20 m66en f26 pciad[23] l2 test[4]* a 15 eeprom_cs c5 ace* d21 vddio g1 int[5] l3 test[3]* a 16 pcst[ 3 ] c6 ce[2]* d22 serr* g2 int[4] l 4 test[2]* a 17 pcst[0] c7 ce[1]* d23 vddin g3 int[3] l5 test[1]* a 18 pciad[ 2 ] c8 dmareq[3] d24 trdy* g4 rxd[0] l22 req[1]* a 19 pciad[ 5 ] c9 vddio d25 vddio g5 vddin l23 vss a 20 c_be[0] c10 bwe[3]* d26 pciad[18] g22 pciad[28] l24 req[2]* a 21 pciad[1 1 ] c11 tdi e1 tclk g23 pciad[27] l25 gnt[2]* a 22 pciad[1 5 ] c12 tms e2 timer[0] g24 pciad[26] l26 pciclk[3] a 23 vss c13 tpc[3] e3 timer[1] g25 pciad[25] m1 oe* a24 vddio c14 pcst[7] e4 vddio g26 pciad[24] m2 wdrst* a 25 irdy * c15 pcst[4] e5 vss h1 txd[0] m3 vddio a 26 c_be [2] c16 pcst[1] e6 sdin[1] h2 rts[0]* m4 vddin b1 pio[3] c17 pciad[1] e7 vddio h3 cts[0]* m5 vss b2 pio[2] c18 vddio e8 vss h4 vddio m22 vss b3 bussprt* c19 pciad[7] e9 dmadone* h5 vss m23 vddio b4 ce[ 6 ] * c20 pciad[9] e10 vss h22 vss m24 req[3]* b5 vddio c21 pciad[13] e11 dmareq[0] h23 vddin m25 gnt[3]* b6 ce[ 3 ]* c22 par e12 vss h24 pciad[29] m26 pciclk[4] b7 dmaack [3] c23 lock* e13 tpc[1] h25 vddio n1 data[1] b8 dmareq[2] c24 devsel* e14 pcst[6] h26 pciclk[0] n2 data[32] b9 dmareq[ 1 ] c25 pciad[17] e15 vss j1 sclk n3 data[0] b10 bwe [2] * c26 pciad[16] e16 trst* j2 txd[1] n4 vss b11 tck d1 pio[7] e17 vss j3 rts[1]* n5 vddio b12 dclk d2 vss e18 vss j4 cts[1]* n22 pme* b13 t do d3 pio[6] e19 vss j5 rxd[1] n23 vddio b14 pcst[8] d4 vddin e20 pciad[10] j22 pciad[31] n24 vss b15 pcst[5] d5 bypasspll* e21 pciad[14] j23 vss n25 data[63] b16 pcst[2] d6 vss e22 vss j24 pciad[30] n26 pciclk[5]
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 10 17 / jan / 02 toshiba corporation p1 data[2] v3 vddio ab5 vss ac21 vss ae11 addr[9] p2 vss v4 vddio ab6 dqm[0] ac22 data[48] ae12 vss p3 data[33] v5 data[7] ab7 vddio ac23 vddin ae13 addr[13] p4 vss v22 vddio ab8 vss ac24 vss ae14 vss p5 vddio v23 data[28] ab9 addr[3] ac25 data[53] ae15 addr[16] p22 vddin v24 vss ab10 vss ac26 data[22] ae16 addr[19] p23 cgreset* v25 data[60] ab11 addr[7] ad1 vddio ae17 sdcs[2]* p24 pll2vcc_a v26 data[29] ab12 vss ad2 data[46] ae18 vss p25 pll2vss_a w1 data[8] ab13 vss ad3 cb[0] ae19 dqm[3] p26 pciclkin w2 data[39] ab14 vss ad4 vss ae20 cb[6] r1 data[35] w3 vss ab15 vss ad5 vss ae21 vddio r2 data[3] w4 vddin ab16 addr[17] ad6 dqm[4] ae22 data[49] r3 data[34] w5 vss ab17 vss ad7 sdcs[1]* ae23 vss r4 vddio w22 vss ab18 sdcs[3]* ad8 vss ae24 vddio r5 vss w23 vddio ab19 vss ad9 vss ae25 data[20] r22 vss w24 vss ab20 dqm[7] ad10 addr[5] ae26 vddio r23 vddin w25 data[27] ab21 cb[3] ad11 vss af1 vss r24 pll1vcc_a w26 data[59] ab22 vss ad12 addr[10] af2 data[47] r25 pll1vss_a y1 data[10] ab23 vddio ad13 addr[12] af3 cb[1] r26 masterclk y2 data[41] ab24 vss ad14 addr[14] af4 cas* t1 vss y3 vss ab25 data[54] ad15 addr[15] af5 vss t2 data[5] y4 data[9] ab26 vss ad16 addr[18] af6 dqm[5] t 3 data[36] y5 data[40] ac1 data[14] ad17 cke af7 addr[0] t 4 vddio y 22 vddio ac2 vss ad18 dqm[6] af8 addr[2] t 5 data[4] y23 data[25] ac3 vss ad19 vss af9 vddio t22 data[30] y24 data[57] ac4 vddin ad20 vss af10 vss t23 data[62] y25 data[26] ac5 vddio ad21 cb[7] af11 vddio t24 vddio y26 data[58] ac6 vss ad22 data[17] af12 addr[11] t25 data[31] aa1 data[43] ac7 sdcs[0]* ad23 vss af13 sdclk[2] t26 vss aa2 data[11] ac8 vddio ad24 data[50] af14 sdclk[0] u1 data[38] aa3 vddio ac9 vddio ad25 data[52] af15 sdclkin u2 data[6] aa4 vss ac10 vddin ad26 data[21] af16 vss u3 data[37] aa5 data[42] ac11 addr[8] ae1 data[15] af17 sdclk[3] u4 vddin aa22 data[23] ac12 vddin ae2 vddio af18 vss u5 vss aa23 vss ac13 vddio ae3 cb[4] af19 sdclk[1] u22 vss aa24 data[55] ac14 vddio ae4 cb[5] af20 vddio u23 vddin aa25 data[24] ac15 vddio ae5 we* af21 data[16] u24 vddio aa26 data[56] ac16 vddio ae6 dqm[1] af22 data[18] u25 data[61] ab1 data[45] ac17 vddin ae7 ras* af23 vddio u26 vss ab2 data[13] ac18 dqm[2] ae8 addr[1] af24 data[19] v1 vss ab3 data[44] ac19 vddin ae9 addr[4] af25 data[51] v2 vss ab4 data[12] ac20 cb[2] ae10 addr[6] af26 vss
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 11 17 / jan / 02 toshiba corporation 3.2 pin layout a b c d e f g h j k l m n 26 a26 b26 c26 d26 e26 f26 g26 h26 j26 k26 l26 m26 n26 25 a25 b25 c25 d25 e25 f25 g25 h25 j25 k25 l25 m25 n25 24 a24 b24 c24 d24 e24 f24 g24 h24 j24 k24 l24 m24 n24 23 a23 b23 c23 d23 e23 f23 g23 h23 j23 k23 l23 m23 n23 22 a22 b22 c22 d22 e22 f22 g22 h22 j22 k22 l22 m22 n22 21 a21 b21 c21 d21 e21 20 a20 b20 c20 d20 e20 19 a19 b19 c19 d19 e19 18 a18 b18 c18 d18 e18 17 a17 b17 c17 d17 e17 16 a16 b16 c16 d16 e16 15 a15 b15 c15 d15 e15 14 a14 b14 c14 d14 e14 13 a13 b13 c13 d13 e13 12 a12 b12 c12 d12 e12 11 a11 b11 c11 d11 e11 10 a10 b10 c10 d10 e10 9 a9 b9 c9 d9 e9 8 a8 b8 c8 d8 e8 7 a7 b7 c7 d7 e7 6 a6 b6 c6 d6 e6 5 a5 b5 c5 d5 e5 f5 g5 h5 j5 k5 l5 m5 n5 4 a4 b4 c4 d4 e4 f4 g4 h4 j4 k4 l4 m4 n4 3 a3 b3 c3 d3 e3 f3 g3 h3 j3 k3 l3 m3 n3 2 a2 b2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 n2 1 a1 b1 c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 n1
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 12 17 / jan / 02 toshiba corporation p r t u v w y aa ab ac ad ae af p26 r26 t26 u26 v26 w26 y26 aa26 ab26 ac26 ad26 ae26 af26 26 p25 r25 t25 u25 v25 w25 y 25 aa25 ab25 ac25 ad25 ae25 af25 25 p24 r24 t24 u24 v24 w24 y24 aa24 ab24 ac24 ad24 ae24 af24 24 p23 r23 t23 u23 v23 w23 y23 aa23 ab23 ac23 ad23 ae23 af23 23 p 2 2 r22 t22 u22 v22 w22 y22 aa22 ab22 ac22 ad22 ae22 af22 22 ab21 ac21 ad21 ae21 af21 21 ab20 ac20 ad20 ae20 af20 20 ab19 ac19 ad19 ae19 af19 19 ab18 ac18 ad18 ae18 af18 18 ab17 ac17 ad17 ae17 af17 17 ab16 ac16 ad16 ae16 af16 16 ab15 ac15 ad15 ae15 af15 15 ab14 ac14 ad14 ae14 af14 14 ab13 ac13 ad13 ae13 af13 13 ab12 ac12 ad12 ae12 af12 12 ab11 ac11 ad11 ae11 af11 11 ab10 ac10 ad10 ae10 af10 10 ab9 ac9 ad9 ae9 af9 9 ab8 ac8 ad8 ae8 af8 8 ab7 ac7 ad7 ae7 af7 7 ab6 ac6 ad6 ae6 af6 6 p5 r5 t5 u5 v5 w5 y5 aa5 ab5 ac5 ad5 ae5 af5 5 p4 r4 t4 u4 v4 w4 y4 aa4 ab4 ac4 ad4 ae4 af4 4 p3 r3 t3 u3 v3 w3 y3 aa3 ab3 ac3 ad3 ae3 af3 3 p2 r2 t2 u2 v2 w2 y2 aa2 ab2 ac2 ad2 ae2 af2 2 p1 r1 t1 u1 v1 w1 y1 aa1 ab1 ac1 ad1 ae1 af1 1
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 13 17 / jan / 02 toshiba corporation 3.3 pin description note: in the i/o columns, ? pu ? indicates an i/o pin with a pull-up resistor, and the term ? o d ? indicates an open drain output . * denotes an active-low signal when used as a suffix to a signal name. signa l name type function sdram / external bus in terface common signals addr[ 19 : 0 ] i/o pu addresses address signal s. for sdram, addr[19:5] are used . when the external bus controller uses these pins, the meaning of each bit varies with the data bus width. the addr signals are also used as boot configuration signals (input) d uring a reset. addr signals are input signals only when the reset * signal is asserted and become output signals after the reset * signal is de- asserted. data[63:0] i/o pu data bus 64-bit data bus. the data[15:0] signals are also used as boot configuration signals (input) d uring a reset. bussprt* o bus separate controls the connection and separation of devices controlled by the external bus controller to or from a high-speed device, such as sdram. h: separate devices other than sdram from the data bus. l: connect devices other than sdram to the data bus. separation and connection are performed using external bi-directional bus buffers (such as the 74xx245).
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 14 17 / jan / 02 toshiba corporation signa l name type function sdram in terface signals sdclk[ 3 :0] o sdram controller clock clock signals used by sdram. the clock frequency is the same as the g-bus clock (gbusclk) frequency. when these clock signals are not used, the pins can be set to h using the sdclk enable field of the configuration register ( ccfg.sdclken[3:0]). sdclkin i/o sdram feedback clock input feedback clock signal for sdram controller input signals. setting the sdclkinen bit of the pin configuration register causes the tx4927 to feed back signals internally, making sdclkin an output signal. cke o clock enable cke signal for sdram. sdcs [ 3:0] * o synchronous memory device chip select chip select signals for sdram. ras* o row address strobe ras signal for sdram . cas* o column address strobe cas signal for sdram . we* o write enable wr signal for sdram .
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 15 17 / jan / 02 toshiba corporation signa l name type function dqm[ 7 :0] o data mask during a read cycle, they control the sdram output buffers. the bits correspond to the following data bus signals: dmq[7] : data[63:54], dmq[6] : data[53:48] dmq[5] : data[47:40], dmq[4] : data[39:32] dmq[3] : data[31:24], dmq[2] : data[23:16] dmq[1] : data[15:8], dmq[0] : data[7:0] cb[7:0] i/o pu ecc control or data parity ecc/parity check bit signals. the bits correspond to the following data bus signals : . cb[7] : data[63:54], cb[6] : data[53:48] cb[5] : data[47:40], cb[4] : data[39:32] cb[3] : data[31:24], cb[2] : data[23:16] cb[1] : data[15:8], cb[0] : data[7:0] cb[7:0] share pins with the pio[15:8] signals for parallel i/o. the boot configuration signal on the addr[18] pin selects between pio[15:8] and cb[7:0].
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 16 17 / jan / 02 toshiba corporation signa l name type function external bus in terface signals sysclk o system clock clock for external i/o devices. output s a clock in f ull speed mode ( at the same frequency as the g-bus clock (gbusclk) frequency ) , half speed mode ( at one half the gbusclk frequency ) , third speed mode (at one third the gbusclk frequency ) , or quarter speed mode (at one quarter the gbusclk frequency ) . the boot configuration signals on the addr[14:13] pins select which speed mode will be used. when this clock signal is not used, the pin can be set to h using the sysclk enable bit of the configuration register (ccfg.sysclken). ace* o address clock enable latch enable signal for the high-order address bits of addr. ce [7:0] * o chip enable chip select signals for rom , sram, and i/o devices. oe* o output enable output enable signal for rom , sram, and i/o devices. swe* o static ram write enable write enable signal for sram and i/o devices. b w e[ 3 :0] * / be[3:0]* o byte write enable / byte enable be[3:0]* indicate valid data position on the data bus data[31:0] at both read and write bus operation. in 16-bit bus mode, be[1:0]* is only used. in 8-bit bus mode, be[0]* is only used. bwe[3:0]* indicate valid data position on the data bus data[31:0] at write bus operation. in 16-bit bus mode, bwe[1:0]* is only used. in 8-bit bus mode, bwe[0]* is only used. the following shows the correspondence between be[3:0]*/bwe[3:0]* and the data bus. be[3]* / bwe[3]* : data[31:24] be[1]* / bwe[1]* : data[15:8] be[2]* / bwe[2]* : data[23:16] be[0]* / bwe[0]* : data[7:0] the function of these signals can be selected from be[3:0]* and bwe[3:0]* by using the data[5] signal and the ebccrn and bc registers in the external bus controller during boot-mode configuration. ack* / ready i/o pu acknowledge flow control signal.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 17 17 / jan / 02 toshiba corporation signa l name type function dma interface dmareq[3:0] i pu dma request dma transfer request signals from an external i/o device. the dmareq [2] signal shares the pin with the acreset * signal. the boot configuration signal on the addr[9] pin selects between dmareq [2] and acreset * . dmaack[3:0] o dma acknowledge dma transfer acknowledge signals to an external i/o device. the dma ack[2] signal shares the pin with the sync signal. the boot configuration signal on the addr[9] pin selects between dma ack[2] and sync. dmadone* i/o pu dma transfer/chain finished dmadone * is either used as an output signal that reports the termination of dma transfer or as an input signal that causes dma transfer to terminate. pci interface pciclk[ 5 :0] o pci clock pc i bus clock signal s . when these clock signals are not used, the pins can be set to h using the pciclk enable field of the pin configuration register ( pcfg.pciclken[5:0]). pciclk in i pci feedback clock input pci feedback clock input. pciad[ 31 : 0] i/o pci address and data multiplexed address and data bus. c_be[ 3 : 0] i/o bus command and byte enable command and b yte e nable signal s .
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 18 17 / jan / 02 toshiba corporation signa l name type function par i/o parity even p arity signal for pciad[31 : 0] and c_be[3 : 0] * . frame* i/o cycle indicates that bus operation is in progress. irdy* i/o initiator ready indicates that the initiator is ready to complete data transfer. trdy* i/o target ready indicates that the initiator is ready to complete data transfer. stop* i/o stop the target sends this signal to the i nitiator to request termination of data transfer. lock* i pci resource clock indicates that the pci bus master is locking (exclusively accessing) a specified memory target on the pci bus. id_sel i initialization device select c hip select signal used for configuration access. devsel* i/o device select the target asserts this signal in response to access from the i nitiator . req[3: 2 ] * i request pci bus signals used by the master to request bus mastership. the boot configuration signal on the data[2] pin determines whether the built-in pci bus arbiter is used. in internal arbiter mode, req [3:2] * are pci bus request input signals . in external arbiter mode, req[ 3:2 ] * are not used. because the pins are still placed in the input state, they must be pulled up externally.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 19 17 / jan / 02 toshiba corporation signa l name type function req[ 1 ] * / inout i/o / od request pci bus signal used by the master to request bus mastership. the boot configuration signal on the data[2] pin determines whether the built-in pci bus arbiter is used. in internal arbiter mode, this signal is a pci bus request input signal . in external arbiter mode, this signal is an external interrupt output signal (intout). req[ 0 ] * i/o request pci bus signal used by the master to request bus mastership. the boot configuration signal on the data[2] pin determines whether the built-in pci bus arbiter is used. in internal arbiter mode, this signal is a pci bus request input signal . in external arbiter mode, this signal is a pci bus request out put signal. gnt[3:0]* i/o grant pci bus indicates that bus mastership has been granted to the pci bus master. the boot configuration signal on the data[2] pin determines whether the built-in pci bus arbiter is used. in internal arbiter mode, all of gnt[3:0] * are pci bus grant output signals . in external arbiter mode, gnt[0] * is a pci bus grant input signal. because gnt[3: 1 ] * also become input signals, they must be pulled up externally. perr* i/o data parity error indicates a data parity error in a bus cycle other than special cycles. serr* i/od system error indicates an address parity error, a data parity error in a special cycle, or a fatal error. in host mode, serr * is an input signal. in satellite mode, serr * is an open-drain output signal. the mode is determined by the boot configuration signal on the addr[19] pin.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 20 17 / jan / 02 toshiba corporation signa l name type function m66en i/o 66mhz clock enable 1: enable 66 mhz operating mode. 0: disable 66 mhz operating mode. in host mode, m66en is an input signal. in satellite mode, m66en is an output signal. the mode is determined by the boot configuration signal on the addr[19] pin. pme* i / od power management event pme * indicates the power management mode. in host mode, pme * is an input signal. in satellite mode, pme * is an open-drain output signal. the mode is determined by the boot configuration signal on the addr[19] pin. eeprom_di i pu eeprom data in this is a data input signal from a serial eeprom for pci configuration. eeprom_do o eeprom data out this is a data output signal to a serial eeprom for pci configuration. eeprom_cs o eeprom chip select this is a chip select signal for a serial eeprom for pci configuration. eeprom_sk o eeprom sk this is a clock signal for a serial eeprom for pci configuration . timer interface timer[1:0] o timer pulse width output timer output signal. tclk i pu external timer clock timer input clock. tmr0, tmr1 and tmr2 share this signal. wdrst* od watchdog reset watchdog reset output signal.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 21 17 / jan / 02 toshiba corporation signa l name type function s io interface cts[1:0] * i pu sio clear to send cts signals. rts[1:0] * o sio request to send rts signals. rxd[1:0] i pu sio receive data serial data input signal. txd[1:0] 3state o sio transmit data serial data output signal. sclk i pu external serial clock input clock for sio0 and sio1. sio0 and sio1 share this signal. pio interface pio[ 15 : 8 ] i/o pu pio ports parallel i/o signals. pio[15: 8 ] share pins with the sdram ecc/parity signals (cb[7:0]). the boot configuration signal on the addr[18] pin selects between pio[15:8] and cb[7:0]. pio[ 7 :0] i/o pio ports parallel i/o signals. pio[ 4 : 2 ] share pins with the ac-link interface signals (sdout, sdin[0], and bitclk). the boot configuration signal on the addr[9] pin selects between pio[4:2] and ac-link interface signals.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 22 17 / jan / 02 toshiba corporation signa l name type function ac-link interface acreset* o ac '97 master h/w reset acreset * shares the pin with the dmareq[2] signal. the boot configuration signal on the addr[9] pin selects between acreset * and dmareq[2].pio[15:8] and cb[7:0]. sync o 48 khz fixed rate sample sync sync shares the pin with the dmaack[2] signal. the boot configuration signal on the addr[9] pin selects between sync and dmaack[2]. sdout o serial, time division multiplexed, ac '97 output stream sdout shares the pin with the pio[4] signal. the boot configuration signal on the addr[9] pin selects between sdout and pio[4]. sdin[1] i serial, t ime d ivision m ultiplexed, ac ? 97 i nput s tream sdin[0] i serial, time division multiplexed, ac '97 input stream sdin[0] shares the pin with the pio[3] signal. the boot configuration signal on the addr[9] pin selects between sdin[0] and pio[3]. bitclk i serial, time division multiplexed, ac '97 input stream bitclk shares the pin with the pio[2] signal. the boot configuration signal on the addr[9] pin selects between bitclk and pio[2]. interrupt signals nmi* i pu non mask - able interrupt non-mask - able interrupt input. int[5:0] i pu external interrupt requests the external interrupt request signals.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 23 17 / jan / 02 toshiba corporation signa l name type function ejtag debug interface tck i pu jtag clock input clock input signal for jtag. tck is used to execute jtag instructions and input/output data. tdi / dint* i pu jtag data input / debug interrupt input when pc trace mode is not selected, this signal is a jtag data input signal. it is used to input serial data to jtag data/instruction registers. when pc trace mode is selected, this signal is an interrupt input signal used to cancel pc trace mode for the debug unit. tdo / tpc[0] o jtag data outpur / pc trace output when pc trace mode is not selected, this signal is a jtag data output signal. data is output by means of serial scan. when pc trace mode is selected, this signal outputs the value of the noncontiguous program counter in sync with the debug clock (dclk). tpc[3:1] o pc trace output tpc[3:1] output the value of the noncontiguous program counter in sync with dclk. tms i pu jtag command tms mainly controls state transition in the tap controller state machine. trst* i test reset input asynchronous reset input for the tap controller and debug support unit. when an ejtag probe is not connected, this pin must be fixed to low. when connecting an ejtag probe, prevent floating, for example, by connecting a pull-up resistor. when this signal is de-asserted, g-bus timeout detection is disabled. dclk o debug clock a clock output for a real-time debug system. the timing of a serial monitor bus and pc trace interface signal are all defined by this debug clock dclk. 3 divide the operation clock of the t mpr 4927 tb at the time of a serial monitor bus operation.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 24 17 / jan / 02 toshiba corporation signa l name type function pcst[8:0] o pc trace status output pc trace status information and the mode of the serial monitor bus. clock signals masterclk i master clock input input pin for the tx4927 operating clock. a crystal resonator cannot be connected to this pin because the pin does not contain an oscillator. haltdoze o halt/doze state output this signal is asserted (high output) when the tx4927 enters halt or doze mode. bypasspll* i pll reset this pin must be fixed to high. cgreset* i cg reset cgreset * initializes the cg reset signals reset* i reset reset signal. test signals t est[4:0]* i pu test mode enable test pins. these pins must be left open or fixed to high.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 25 17 / jan / 02 toshiba corporation signa l name type function power pins and total pin count pll 1 v dd _ a , pll2vdd_a, pll 1 vss_a, pll2vss_a - power and ground pins to internal pll circuit . pll1vcc_a and pll2vcc_a = 1.5v, pll1_vss_a and pll2_vss_a = gnd v dd i n - internal power pins power pins at 1.5 v v dd io - i/o power pins power pins at 3.3v vss - ground digital ground pins. vss = 0 v.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 26 17 / jan / 02 toshiba corporation 4. pin multiplexing a total of 13 pins of the tx4927 have multiplexed functions. table 4.1 shows the multiplexed pins. the function of a given pin is selected in various ways, depending on the pin(s) involved. table 4.2 and table 4.3 show the setting by booting of tx4927. table 4.1 pin multiplexing signal name multiplexed function cb[7:0] cb[7:0] / pio[15:8] dmareq[2] dmareq[2] / acreset* dmaack[2] dmaack[2] / sync pio[4:2] pio[4:2] / sdout, sdin[0], bitclk table 4.2 setting by addr[18] table 4.3 setting by addr[9] signal name addr[9]=1 (aclc) addr[9]=0 (non aclc) dmareq[2] o acreset* i dmareq[2] dmaack[2] o sync o dmaack[2] pio[4] o sdout i/o pio[4] pio[3] i sdin[0] i/o pio[3] pio[2] i bitclk i/o pio[2] signal name addr[18]=0 (non ecc) addr[18]=1 (ecc) cb[7:0] i/o pio[15:8] i/o cb[7:0]
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 27 17 / jan / 02 toshiba corporation 5. electrical characteristics 5.1 absolute maximum rating (*1) param e ter symbol rating unit supply voltage (for i/o) v ddio max - 0.3 to 3.9 v supply voltage (for internal) v ccintmax - 0.3 to 3.0 v input voltage (*2) v in - 0.3 to v ddio + 0.3v v storage temperature t stg - 40 to +125 c power p d 1.5 ( typ.) w note) (*1) if lsi is used above the maximum ratings, permanent destruction of lsi can result. in addition, it is desirable to use lsi for normal operation under the recommended condition. if these conditions are exceeded, reliability of lsi may be adversely affected. (*2) the maximum rated v ddiomax voltage must not be exceeded even at v ddio + 0.3 volts. 5.2 recommended operating conditions (*3) parameter symbol condition min. max. unit i/o v ddio 3. 1 3. 5 v supply voltage internal v ddin 1.4 1.6 v operating case temperature t c 0 70 c (*3) functional operation should be restricted to the recommended operating conditions. those are the limits under which proper device operation is guaranteed. therefore, the end product must be designed within the recommended voltage and temperature ranges indicated.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 28 17 / jan / 02 toshiba corporation 5.3 dc characteristics dc characteristics except for pci interface (tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) parameter sym conditions m in . m ax . unit low-level input voltage v il1 (*1) -0.3 0.8 v high-level input voltage v ih1 (*1) 2.0 v ddio+ 0. 3 v low-level output current i ol1 i ol 2 (*2) v ol =0.4v (*3) v ol =0.4v 8 4 - - ma ma low-level output current i ol 3 i ol 4 (*4) v ol =0.4v (*5) v ol =0.4v 16 8 - - ma ma high-level output current i oh1 i oh2 (*2) v oh =2.4v (*3) v oh =2.4v - - -8 -4 ma ma high-level output current i oh 3 i oh 4 (*4) v oh =2.4v (*5) v oh =2.4v - - -16 -8 ma ma low-level input leakage current i il 1 i il 2 (*6) v in = v ss (*7) v in = v ss -10 - 200 10 -10 m a m a high-level input leakage current i ih1 i ih2 (*8) v in =v ccio (*9) v in =v ccio -10 10 10 200 m a m a hi-z output leakage current i oz (*10) -10 10 m a operating current (for internal) i cc int vddio = 3. 3 v, vddin = 1.6v, masterclk=100mhz pclock = 200mhz 600 ma operating current (for i/o) i cc io vddio = 3. 5 v, vddin = 1.5v, masterclk=100mhz pclock = 200mhz load=25pf 160 ma (*1) all input and input-mode bidirectional pins except pci interface signals (*2) ace*, ack*, bussprt*, bwe[3:0]*, ce[7:0]*, dmaack[3:0], dmadone*, eeprom_cs, eeprom_do, eeprom_sk, haltdoze, pio[7:0], rts[1:0], swe*, sysclk, timer[1:0], txd[1:0] (*3) dclk, pcst[8:0], tdo, tpc[3:1] (*4) applies to addr[19:0], cas*, cb[7:0], cke, data[63:0], dqm[7:0], oe*, ras*, sdclk[3:0], sdclkin, sdcs[3:0]* and we when an output buffer drive strength of 16 ma is used. (*5) drive 8ma: addr[19:0], cas*, cb[7:0], cke, data[63:0], dqm[7:0], oe*, ras*, sdclk[3:0], sdclkin, sdcs[3:0]*, we (*6) eeprom_di, cgreset*, reset*, trst*, bypasspll*, masterclk, dmadone*, pio[7:0], sdclkin (*7) cts[1:0]*, dmareq[3:0], rxd[1:0], sclk, tclk, int[5:0], tck, tdi, test[4:0]*, tms, ack*, cb[7:0], data[63:0], addr[19:0], nmi* (*8) (*6), (*7) signals except for trst* (*9) trst* (*10) txd[1:0]
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 29 17 / jan / 02 toshiba corporation dc characteristics except for pci interface ( tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) parameter sym conditions m in . max. unit low-level input voltage v ilpci (*1) -0. 5 0.9 v high-level input voltage v ih pci (*1) 1.8 v ddio+ 0. 3 v high-level output voltage v oh pci (*2) i out = - 500ua v ddio 0.9 - v low-level output voltage v ol pci (*2) i o ut = 1500ua - v ddio 0.1 v input leakage current i ih pci i il pci 0 < v in < vddio - 10 - 10 10 10 m a m a hi-z output leakage current i ozpci (*3) - 10 10 m a (*1) id_sel, pciclkin, c_ be[3:0], devsel*, frame*, gnt[3:0]*, irdy*, lock*, m66en, par, pciad[31:0], perr*, req[3:0], serr*, stop*, trdy* (*2) id_sel, pciclkin (*3) pciclk[5:0], pme* power circuit for pll recommended circuit for pll note) c1, cs, c3, r and l should be placed as closed to the processor as possible. parameter symbol as a reference value unit resistor r 5 ohm inductance l t.b.d. m h capacitor c1 c2 c3 1 82 10 n f n f m f vddin, pll1vdd_a, pll2vdd_a 1.5v 0.1v v c3 t x4927 l r c1 c2 l r vss vddin l r vss v ddin pll1vdd_a pll2 v dd_a p ll2vss_a l r c3 c2 c1 pl l1vss_a
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 30 17 / jan / 02 toshiba corporation 5.5 ac characteristics masterclk ac characteristics ( tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) param e ter sym condition min. max. unit masterclk period t mcp addr[2]=h in boot time 10 80 ns masterclk frequency (*1) f mck addr[2]=h in boot time 12.5 100 mhz masterclk high t mch 3 ns masterclk low t mcl 3 ns internal operating frequency f cpu 5 0 200 mhz masterclk rise time t mcr 2 ns masterclk fa ll time t mcf 2 ns (*1) proper circuit operation of the tx4927 is guaranteed only when power supply to it is stable and the on-chip pll is enabled. power on ac characteristics ( tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) param e ter sym condition min. max. unit pll stable time t mcp_pll 10 ms cgreset* width time t mck_pll 1 ms reset* width time t mc h_pll 1 - ms t mcp _pll t mck _pll masterclk stable time t mch_pll vddin, vddio, pll1vdd_a, pll2vdd_a masterclk cgreset * reset * t mch t mcl m a s ter clk 0.8 v ddio 0.2 v ddio t mcr t mcf t m c p
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 31 17 / jan / 02 toshiba corporation sdram interface ac characteristics ( tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) signal name i/o load ( pf) buffer type sym descriptions min (ns) max (ns) tcyc_sdclk clock cycle time 10 - thigh_sdclk clock high time 3 - sdclk[3:0] o 50 16ma tlow_sdclk clock low time 3 - sdclkin i - - tbp clock input timing ( non bypass mode ) 0 4.0 addr[19:5] o 150 16ma tval_addr1 address output delay (*1) 1. 5 6.5 sdcs[3:0]* o 100 16ma tval_sdcs output delay for chip select 1.5 6.5 ras* o 150 16ma tval_ras output delay for ras* (*1) 1.5 6.5 cas* o 150 16ma tval_cas output delay for cas* (2 cycle bus operation) 1.5 6.5 we* o 150 16ma tval_we output delay for write enable (2 cycle bus operation) 1.5 6.5 cke o 150 16ma tval_cke output delay for clock enable 1.5 6.5 dqm[7:0] o 50 16ma tval_dqm output delay for data mask (*1) 1.5 6.5 tval_data1 output delay for data ( high <->low) (*1) 1.5 6.5 tval_data1v output delay for data ( hi-z -> valid) 1.5 6.5 50 16ma tval_data1z output delay for data ( valid->hi-z) 1.5 6.5 tsu_data1b data setup time (bypass mode) 4.0 - th_data1b data hold time (bypass mode) 0.5 - tsu_data1n b data setup time (non bypass mode) 1.5 - data[63:0] i/o - - th_data1nb data hold time (non bypass mode) 1.0 - (*1) an sdram bus transaction can complete in no more than two clock cycles through programming the sdramc and configuration registers.
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 32 17 / jan / 02 toshiba corporation tval_* sdclk output input th_* tsu_* outputs valid inputs valid output signals and when bypass mode input signals (sdclk basis) sdclkin input th_* tsu_* sdclk tbp inputs valid when non bypass mode input signals (sdclk basis)
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 33 17 / jan / 02 toshiba corporation external bus interface ac characteristics ( tc = 0 ~ 70 c, v ddio = 3.3v 0.2v , v ddin = 1 .5v 0.1v , v ss = 0v) signal name i/o load ( pf) buffer type sym descriptions min (ns) max (ns) tcyc_sysclk clock cycle time 10 - thigh_sysclk clock high time 4 - sysclk o 50 8ma(fix) tlow_sysclk clock low time 4 - addr[19:5] o 150 16ma tval_addr2 output delay for address 1. 5 6.5 ce[7:0]* o 50 8ma(fix) tval_ce output delay for chip enable 1.5 8.5 oe* o 50 8ma(fix) tval_oe output delay for output enable 1.5 8.5 swe* o 50 8ma(fix) tval_swe output delay for write enable 1.5 8.5 bwe*[3:0] o 50 8ma(fix) tval_bwe output delay for byte enable 1.5 8.5 ace* o 50 8ma(fix) tval_ace output delay for address clock enable 1.5 8.5 bussprt* o 50 8ma(fix) tval_bus output delay for bus separate 1.5 8.5 tval_data2 output delay for data (high <-> low) 1.5 6.5 tval_data2v output delay for data (hi-z -> valid) 1.5 8.5 50 16ma tval_data2z output delay for data (valid -> hi-z) 1.5 8.5 tsu_data2 data setup time 6.0 - data[31:0] i/o - - th_data2 data hold time 0.5 - tval_ack output delay for ack* (high <-> low) 1.5 8.5 tval_ackv output delay for ack* (hi-z -> valid) 1.5 6 .5 50 8ma(fix) tval_ackz output delay for ack* ( valid -> hi-z) 1.5 8.5 tsu_ack ack* setup time 6.0 - ack* i/o - - th_ack ack* hold time 0.5 - tval_* sysclk output input th_* tsu_* inputs valid outputs valid tcyc_sysclk thigh_sysclk tlow_sysclk external bus interface
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 34 17 / jan / 02 toshiba corporation pci interface ac characteristics signal name i/o pci-bus spec. load ( pf) sym descriptions min (ns) max (ns) tcyc66 input clock cycle time 15 30 thigh66 input clock high time 6 - tlow66 input clock low time 6 - 66mhz - tslew66 input clock through rate [v/ns] 1.5 4 tcyc33 input clock cycle time 30 40 thigh33 input clock high time 11 - tlow33 input clock low time 11 - pciclkin i 33mhz - tslew33 input clock through rate [v/ns] 1 4 tcyco66 output clock cycle time 15 30 thigho66 output clock high time 6 - 66mhz 50 tlowo66 output clock low time 6 - tcyco33 output clock cycle time 30 40 thigho33 output clock high time 11 - 33mhz 70 tlowo33 output clock low time 11 - pciclk[5:0] o - 50 tskw output clock slew (point to point connection) 0 tbd 30 tval66 output delay (bus connection) 2 8 - tsu66 setup time (bus connection) 3 (tbd) - 66mhz - th66 hold time (bus connection) 0.5 - 70 tval33 output delay (bus connection) 2 8 - tsu33 setup time (bus connection) 5 - pciad[31 :0 ] c_be[3 :0 ] par frame* irdy* trdy* stop* devsel* perr* serr* lock* m66en pme* i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o o 3 33mhz - th33 hold time (bus connection) 0 - 30 tppd66 output delay (point to point connection) 2 11 - tpps66 setup time (point to point connection) 7 - 66mhz - tpph66 hold time (point to point connection) 0.5 - 70 tppd33 output delay (point to point connection) 2 12 - tpps33 setup time (point to point connection) 10 - id_sel req[3:0]* gnt[3:0]* i i/o i/o 33mhz - tpph33 hold time (point to point connection) 0 -
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 35 17 / jan / 02 toshiba corporation tlow66/tlow33 thigh66/thigh33 tcyc66/tcyc33 0.4 vcc 0.5 vcc 0.3 vcc 0.6 vcc 0.2 vcc 0.4 vcc p-to-p ( minimum) (vcc=3.3v) tsu66/tsu33/tpps66/tpps33 th66/th33/tpph66/tpph33 tval66/tval33/tppd66/tppd33 input output inputs valid outputs valid tslew66/tslew33 pciclkin pci interface (3.3v) tskw pciclk[n] pciclk [except for n ] n=0 to 5 tcyco66/tcyco33 thigho66/thigho33 tlowo66/tlowo33 pci clock skew
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 36 17 / jan / 02 toshiba corporation 6. package
integrated circuit toshiba risc p rocessor tmpr49 27atb-200 ejc-tmpr49 27atb - 37 17 / jan / 02 toshiba corporation 7. history 28/aug/ 00 modify the description for sdram controller modify pin layout modify from dfs signal to test2 signal 13/jan/ 01 added the package diagram 22/jan/01 dc/ac timing 26/jan/ 01 modify the description 6/feb/ 01 modify the description 20/aug/ 01 modify the signal description and ac characteristics 17/jan/ 02 modify the product name tmpr4927tb -> TMPR4927ATB-200 modify the spec of ac and dc

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